Features: `High-performance CMOS nonvolatile static RAM 32768 x 8 bits
`25 ns Access Times
`10 ns Output Enable Access Times
`Software STORE Initiation
`Automatic STORE Timing
`106 STORE cycles to EEPROM
`100 years data retention in EEPROM
`Automatic RECALL on Power Up
`Software RECALL Initiation
`Unlimited RECALL cycles from EEPROM
`Unlimited Read and Write to SRAM
`Single 5 V ± 10 % Operation
`Operating temperature ranges:
0 to 70
-40 to 85
`QS 9000 Quality Standard
`ESD protection > 2000 V (MIL STD 883C M3015.7-HBM)
`RoHS compliance and Pb- free Package: SOP28 (330 mil)
Pinout
Specifications
| Absolute Maximum Ratingsa |
Symbol |
Min. |
Max. |
Unit |
Power Supply Voltage
Input Voltage |
VCC
VI |
-0.5
-0.3 |
7
VCC+0.5 |
V
V |
Output Voltage
Power Dissipation |
VO
PD |
-0.3
|
VCC+0.5
1 |
V
W |
Operating Temperature C-Type
K-Type |
Ta |
0
-40 |
70
85 |
|
| Storage Temperature |
Tstg |
-65 |
150 |
|
a: Stresses greater than those listed under ''Absolute Maximum Ratings'' may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DescriptionThe U631H256 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions of U631H256 are disabled.
The U631H256 is a fast static RAM (25 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM U631H256 can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through software sequences.
The U631H256 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity.
Once a STORE cycle U631H256 is initiated, further input or output are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE U631H256 initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted.
Internally, RECALL U631H256 is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells.
The RECALL U631H256 operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.
The U631H256 is pin compatible with standard SRAMs.
U631H256 Data Sheet
