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Part Number: UPD16835AGG
Description: The µPD16835A is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a ...
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UPD16835AGG
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General Description
UPD16835AGG General Description
The µPD16835A is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FEToutput circuit. Because it uses MOS FETs in its output stage, this driver IC onsumes less power than conventionaldriver ICs that use bipolar transistors.Because the µPD16835A controls a motor by inputting serial data, its package has been shrunk and the numberof pins reduced. As a result, the performance of the application set can be improved and the size of the set has beenreduced.The µPD16835A employs a current-controlled 64-step micro step driving method that drives stepper motor withlow vibration.The µPD16835A is housed in a 38-pin plastic shrink SOP to contribute to the miniaturization of the application set.The µPD16835A can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.
UPD16835AGG Maximum Ratings
| Parameter | Symbol | Condition | Rating | Unit |
| Supply voltage | VDD | 0.5 to +6.0 | V | |
| VM | 0.5 to +11.2 | V | ||
| Input voltage | VIN | 0.5 to VDD+ 0.5 | V | |
| Reference voltage | VREF | 500 | mV | |
| H bridge drive current | IM(DC) | DC | ±150 | mA/phase |
| Instantaneous H bridge drive current Note 1 |
IM(pulse) | PW 10 ms, Duty 5% | ±300 | mA/phase |
| Power consumption Note 2 | PT | 1.0 | W | |
| Peak junction temperature | TCH(MAX.) | 150 | °C | |
| Storage temperature | Tstg | 55 to +150 | °C |
UPD16835AGG Features
•Four H bridge circuits employing power MOS FETs
•Current-controlled 64-step micro step driving
•Motor control by serial data (8 bytes x 8 bits) (original oscillation: 4-MHz input)Data is input with the LSB first.EVR reference setting voltage: 100 to 250 mV (@VREF = 250 mV) ... 4-bit data input (10-mV step)Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step)Original oscillation division or internal oscillation selectableNumber of pulses in 1 VD: 0 to 252 pulses ... 6 bits + 2-bit data input (4 pulses/step)Step cycle: 0.25 to 8191.75 µs ... 15-bit data input (0.25- µs step)
•3-V power supply. Minimum operating voltage: 2.7 V (MIN.)
•Low current consumption IDD: 3.0 mA (MAX.), IDD RESET): 100 µA (MAX.), IMO(RESET): 1.0 µA (MAX.)
•38-pin plastic shrink SOP (7.62 mm (300))
UPD16835AGG Connection Diagram
UPD100500D-15
PDF/DataSheet Download
- Datasheet: UPD100500D-15
- File Size: 101698 KB
- Manufacturer:
- Click here to Download
- ·UPD100500D-20
- x1 SRAM
- 101698 KB
- ·UPD100504D-15
- x4 SRAM
- 101162 KB
- ·UPD10500D-15
- x1 SRAM
- 108645 KB
- ·UPD10500D-20
- x1 SRAM
- 108645 KB
- ·UPD10504D-15
- x4 SRAM
- 107973 KB
- ·UPD120N
- NEC [NEC]
- THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A)
- 161162 KB
- ·UPD120N15T1B
- NEC [NEC]
- THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A)
- 161162 KB
- ·UPD120N15T1B-E1
- NEC [NEC]
- THREE-TERMINAL LOW-DROPOUT POSITIVE-VOLTAGE REGULATOR (OUTPUT CURRENT: 0.3 A)
- 161162 KB
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