Purchase UPD178004, In-stock UPD178004 From SeekIC.
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UPD178004
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DataSheet
General Description
UPD178004 Maximum Ratings
| Parameter | Symbol | Test Conditions | Rating | Unit | |
| Power supply voltage | VDD | -0.3 to +7.0 |
V | ||
| Input voltage | VI1 | Excluding P60 to P63 | 0.3 ~ VDD+0.3 | V | |
| V12 | P60 to P63 |
N-ch Open-drain | 0.3 ~ VDD+16 | V | |
| Output voltage | VO | 0.3 ~ VDD+0.3 | V | ||
| Output withstand voltage | VBDS | P132 to P134 | N-ch Open-drain | 16 | V |
| Analog input voltage | VAN | P10 to P15 | Analog input pin | 0.3 to VDD + 0.3 | V |
| Output current high | IOH | 1 pin | 10 | mA | |
P01 to P06, P30 to P37, P56, P57, P60 to P67,P120 to P125 total |
15 | mA | |||
| P10 to P15, P20 to P27, P40 to P47, P50 to P55,P132 to P134 total | 15 | mA | |||
| Output current low | IOL Note | 1 pin | Peak value | 15 | mA |
| Effective value | 7.5 | mA | |||
Operating ambient temperature |
TA | 40 to +85 | °C | ||
| Storage temperature | Tstg | 40 to +85 | °C | ||
UPD178004 Features
• Internal high-capacity ROM and RAM
• Instruction Cycle: 0.44 ms (4.5-MHz crystal oscillator used)
• Large array of on-chip peripheral hardware General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear circuits.
• On-chip hardware for a PLL frequency synthesizer. Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.
• Vector Interrupts: 17
• Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation)
VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower)
VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)
• Instruction Cycle: 0.44 ms (4.5-MHz crystal oscillator used)
• Large array of on-chip peripheral hardware General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear circuits.
• On-chip hardware for a PLL frequency synthesizer. Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.
• Vector Interrupts: 17
• Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation)
VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower)
VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)
UPD178004 Typical Application
Car stereo, home stereo systems.
UPD178004 Connection Diagram
UPD178004AGC
PDF/DataSheet Download
- Datasheet: UPD178004AGC
- File Size: 321694 KB
- Manufacturer: NEC [NEC]
- Click here to Download
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