UPD98409

Features:

Conforms to ATM Forum
PCI bus interface (5/3.3 V, 32/64 bits, 33 MHz) Conforms to PCI Local Bus Specification Revision 2.1
AAL-5 SAR sublayer and ATM layer functions
Hardware support of AAL-5 processing (non-AAL-5 processing can be supported in software)
Supports up to 64 virtual channels (VC) (64-VC control memory)
Two traffic shapers for transmission scheduling
MPEG packet transfer engine mitigating the workload of compressed image data transfer by CPU
Receive FIFO of 12 cells
PHY device I/F: UTOPIA Level-1 interface (octet/cell level handshake)
JTAG boundary scan test functions
0.35-m CMOS process, +5/+3.3-V power supply
   -  Bus interface +5 V :  +5/+3.3-V power supply
   -  Bus interface +3.3 V:  +3.3-V single power supply


Pinout




Specifications

Parameter	Symbol	Conditions	Ratings	Unit
Supply voltage	VDD3		-0.5 to +4.6	V
	VDD5Note	VDD3 VDD5	-0.5 to +6.6	V
Input voltage	VI	Except pin PCI, VI < VDD3 + 3.0 V	-0.5 to +6.6	V
		PCI pin	5.5 to +11.0	V
Output voltage	VO	Except PCI pin and PO0-PO3, VO < VDD3 + 3.0 V	-0.5 to +6.6	V
		PO3-PO0, VO < VDD3 + 0.5 V	-0.5 to +4.6	V
		PCI pin	-0.5 to +6.6	V
Output current	IO	Except PCI pin and PO0-PO3	20	mA
		PO3-PO0	40	mA
		PCI pin	20	mA
Operating ambient temperature	TA		0 to +70	°C
Storage temperature	Tstg		-65 to +150	°C

Description

The PD98409 (NEASCOT-S40C^TM) is a high-performance SAR chip for segmentation and reassembly of ATM cells.  Provided with a PCI (Peripheral Component Interconnect) bus interface control memory and supporting a MPEG packet transfer engine function to mitigate the workload of the CPU in transferring compressed image data,this chip has ideal specifications for use in a set top box (STB) to interface with an ATM network.  The PD98409 conforms to ATM Forum recommendations and has AAL5-SAR sublayer and ATM layer functions.