UPD98405

Features:

Conforms to ATM Forum.
Host bus interface supporting PCI bus/generic bus.
   - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1
   - Generic bus interface (5/3.3 V, 32 bits, 33 MHz)
AAL-5 SAR sublayer, ATM layer, and TC sublayer functions
Hardware support of AAL-5 processing
Software support of non-AAL-5 traffic
SONET STS-3c/SDH STM-1 155-Mbps framer function
Clock recovery/clock synthesizer function
Supports up to 32 K virtual channels (VCs)
Sixteen traffic shapers for VBR for transmission scheduling
Hardware support of CBR/VBR/ABR/UBR service
Supports multi-cell burst transfer for transmission and reception
MIB counter function
Supports LAN emulation function
Receive FIFO of 96 cells
External PHY devices connectable: UTOPIA Level-1 interface
0.35-m CMOS process, +5-/3.3-V power supply
   - Bus interface +5 V: +5-/3.3-V power supply
   - Bus interface +3.3 V: +3.3-V power supply
304-pin plastic QFP


Pinout




Specifications

Parameter	Symbol	Condition	Rating	Unit
Supply voltage	VDD		0.5 to +4.6	V
	VDD5Note1		0.5 to +6.5	V
Input/output voltage	VI/VO	Normal I/O pin	0.5 to +6.6	V
		PCI I/O pinNote2	0.5 to +6.6	V
		P-ECL pin	0.5 to +4.6 and VDD + 0.5	V
Ambient operating frequency	TA		0 to +70	°C
Storage temperature	Tstg		65 to +150	°C

Description

The PD98405 (NEASCOT-S20^TM ) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells.  It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware.  The PD98405 conforms to ATM Forum and has the functions of the AAL-5 SAR sublayer, ATM layer, and TC sublayer.