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UPD98404

Features: On-chip clock recovery/clock synthesis functionsProvides TC sub-layer function for the ATM protocol's physical layerSupported frame formats include 155 Mbps SONET STS-3c/SDH STM-1Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995)Supports three UTOPIA interfac...

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SeekIC No. : 004538333 Detail

UPD98404: Features: On-chip clock recovery/clock synthesis functionsProvides TC sub-layer function for the ATM protocol's physical layerSupported frame formats include 155 Mbps SONET STS-3c/SDH STM-1Conforms ...

UPD98404 Data Sheet

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Part Number:
UPD98404
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

On-chip clock recovery/clock synthesis functions
Provides TC sub-layer function for the ATM protocol's physical layer
Supported frame formats include 155 Mbps SONET STS-3c/SDH STM-1
Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995)Supports three UTOPIA interfaces:
Single PHY octet-level handshaking
Single PHY cell-level handshaking
Multi PHY mode
Selectable to drop/bypass unassigned cells
On-chip internal loopback functions for PMD layer loopback and ATM layer loopback
Supports two PMD interfaces:  serial and parallel
155.52 Mbps serial interface
19.44 MHz parallel interface
Provides registers for writing/reading overhead information
                 SOH (section overhead) :J0 byte, Z0 (first and second) bytes, F1 byte
                 LOH (line overhead) :K1 byte, K2 byte
                 POH (path overhead) :F2 byte, C2 byte, H4 byte
Provides pseudo error frame transmit function for various errors
Supports JTAG boundary scan test function (IEEE 1149.1)
CMOS technology
+3.3 V single power supply


Pinout

Connection Diagram


Specifications

Item Symbol Condition Ratings Unit
Power supply voltage VDD   0.5 to +4.6 V
Input/output voltage VI1/VO1 Pin other than P-ECL, analog level 0.5 to +6.6 or VDD +3.0 V
VI2/VO2 P-ECL, analog level 0.5 to +4.6 or VDD +0.5 V
Operating temperature TA   45 to +85 °C
Storage temperature Tstg   65 to +150 °C



Description

The PD98404 NEASCOT-P30TMis an LSI for ATM applications, which can be used in ATM adapter boards for connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches.  This LSI provides the TC sub-layer functions in the SONET/SDH-base physical layer within the ATM protocol defined by the ATM Forum's UNI3.1 recommendations.

This PD98404 NEASCOT-P30TM product's main functions include transmission functions such as mapping of ATM cells sent from the ATM ayer to the payload field in a 155 Mbps SONET STS-3c/SDH STM-1 frame and transmission to PMD (Physical Media Dependent) sub-layer in the physical layer.  Its reception functions include separation of the overhead from the ATM cells in data streams received from PMD sub-layer and transmission of the ATM cells to the ATM layer.  In addition, this LSI includes a clock recovery function that extracts a reception sync clock from bit streams in received data and a clock synthesis function that generates a clock for transmissions.




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