V53C16129H

Features: 128K x 16-bit organization EDO Page Mode for a sustained data rate of 67 MHzn RAS access time: 40, 45, 50, 60 ns Dual CAS Inputs Low Power Dissipation Read-Modify-Write, RAS-Only Refresh,CAS-Before-RAS Refresh Refresh Interval: 512 cycles/8ms Available in 40-pin 400 mil SOJ and 40/44L-pi...

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SeekIC No. : 004539922 Detail

V53C16129H: Features: 128K x 16-bit organization EDO Page Mode for a sustained data rate of 67 MHzn RAS access time: 40, 45, 50, 60 ns Dual CAS Inputs Low Power Dissipation Read-Modify-Write, RAS-Only Refresh,C...

floor Price/Ceiling Price

Part Number:
V53C16129H
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Description



Features:

 128K x 16-bit organization 
EDO Page Mode for a sustained data rate of 67 MHz n RAS access time: 40, 45, 50, 60 ns 
Dual CAS Inputs 
Low Power Dissipation 
Read-Modify-Write, RAS-Only Refresh,CAS-Before-RAS Refresh 
Refresh Interval: 512 cycles/8ms 
Available in 40-pin 400 mil SOJ and 40/44L-pin400 mil TSOP-II packages 
Single +5V± 10% Power Supply
 TTL Interface



Pinout

  Connection Diagram




Specifications

Ambient TemperatureUnder Bias.................................................. 10°C to +80°C
Storage Temperature (plastic).................................................... 55°C to +125°C
Voltage Relative to VSS .................................................................1.0 V to +7.0 V
Data Output Current .................................................................................... 50 mA
Power Dissipation.......................................................................................... 1.0 W



Description

The V53C16129H is a 131,072 x 16 bit highperformance CMOS dynamic random access memory. The V53C16129H offers Page mode with Extended Data Output. EDO Page Mode operation allows random access up to 512 x 16 bits, within a page, with cycle times as short as 15 ns. An address, CAS and RAS input capacitances are reduced to minimize the loading. The V53C16129H has asymmetric address 8-bit row and 9-bit column.

All inputs are TTL compatible. The V53C16129H is best suited for graphics, and DSP applications requiring high performance memories.




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