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V53C16258L

Features: 256K x 16-bit organizationEDO Page Mode for a sustained data rate of 71 MHzRAS access time: 35, 40, 45, 50 nsDualCAS Inputs Low power dissipation Read-Modify-Write,RAS-Only Refresh,CAS-Before-RAS Refresh, and Self Refresh Optional Self Refresh (V53C16258SL) Refresh Interval: Standard: 51...

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SeekIC No. : 004539927 Detail

V53C16258L: Features: 256K x 16-bit organizationEDO Page Mode for a sustained data rate of 71 MHzRAS access time: 35, 40, 45, 50 nsDualCAS Inputs Low power dissipation Read-Modify-Write,RAS-Only Refresh,CAS-Bef...

V53C16258L Data Sheet

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Part Number:
V53C16258L
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 256K x 16-bit organization
 EDO Page Mode for a sustained data rate of 71 MHz 
 RAS access time: 35, 40, 45, 50 ns
 Dual CAS Inputs 
Low power dissipation 
Read-Modify-Write,RAS-Only Refresh,CAS-Before-RAS Refresh, and Self Refresh 
Optional Self Refresh (V53C16258SL) 
Refresh Interval: Standard: 512 cycles/8ms 
Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages
 Single +3.3V±0.3V Power Supply 
TTL Interface


Pinout

Connection Diagram




Specifications

Ambient TemperatureUnder Bias.......................................................................... 10°C to +80°C
Storage Temperature (plastic)............................................................................ 55°C to +125°C
Voltage Relative to VSS .........................................................................................1.0 V to +4.6 V
Data Output Current ............................................................................................................ 50 mA
Power Dissipation.................................................................................................................. 1.0 W


Description

The V53C16258L is a 262,144 x 16 bit highperformance CMOS dynamic random access memory. The V53C16258L offers Page mode with
Extended Data Output. An address, CAS and RAS input capacitances are reduced to one quarter when the x4 DRAM is used to construct the same memory density. The V53C16258L has symmetric address and accepts 512 cycle 8ms interval.

All inputs are TTL compatible. EDO Page Mode operation allows random access up to 512 x 16 bits, within a page, with cycle times as short as 15ns.

The V53C16258L is ideally suited for a wide variety of high performance portable computer systems and peripheral applications.




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