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V53C818H

Features: 512K x 16-bit organizationEDO Page Mode for a sustained data rate of83 MHzRAS access time: 30, 35, 40, 45, 50 nsDualCAS InputsPin-to-Pin compatible with 256K x 16Low power dissipationRead-Modify-Write, RAS-Only Refresh,CAS-Before-RAS RefreshRefresh Interval: 512 cycles/8 msAvailable in 4...

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SeekIC No. : 004539948 Detail

V53C818H: Features: 512K x 16-bit organizationEDO Page Mode for a sustained data rate of83 MHzRAS access time: 30, 35, 40, 45, 50 nsDualCAS InputsPin-to-Pin compatible with 256K x 16Low power dissipationRead-...

V53C818H Data Sheet

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Part Number:
V53C818H
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 512K x 16-bit organization
 EDO Page Mode for a sustained data rate of83 MHz
 RAS access time: 30, 35, 40, 45, 50 ns
 Dual CAS Inputs
 Pin-to-Pin compatible with 256K x 16
 Low power dissipation
 Read-Modify-Write, RAS-Only Refresh,CAS-Before-RAS Refresh
 Refresh Interval: 512 cycles/8 ms
 Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages
 Single +5V±10% Power Supply
 TTL Interface


Pinout

Connection Diagram




Specifications

Ambient TemperatureUnder Bias................................................................... 10°C to +80°C
Storage Temperature (plastic).................................................................... 55°C to +125 °C
Voltage Relative to VSS ..................................................................................1.0 V to +7.0 V
Data Output Current .................................................................................................... 50 mA
Power Dissipation.......................................................................................................... 1.4 W


Description

The V53C818H is a 524,288 x 16 bit highperformance CMOS dynamic random access memory. It offers Page mode operation with Extended Data Output. An address, CAS and RAS input capacitances are reduced to one half when the 256K x 16 DRAM is used to construct the same memory density. The V53C818H has asymmetric address, 10-bit row and 9-bit column.

All inputs are TTL compatible. EDO Page Mode operation allows random access up to 512 x 16 bits, within a page, with cycle times as short as 15ns. The V53C818H is ideally suited for graphics, digital signal processing and high performance peripherals.




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