V53C8258H

Features: 256K x 8-bit organizationEDO Page Mode for a sustained data rateof 71 MHzRAS access time: 35, 40, 45, 50 nsLow power dissipationRead-Modify-Write, RAS-Only Refresh,CAS-Before-RAS Refresh capabilityRefresh Interval: 512 cycles/8 msAvailable in 24 pin 300 mil Plastic DIP,26/24 pin 300 mil ...

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SeekIC No. : 004539950 Detail

V53C8258H: Features: 256K x 8-bit organizationEDO Page Mode for a sustained data rateof 71 MHzRAS access time: 35, 40, 45, 50 nsLow power dissipationRead-Modify-Write, RAS-Only Refresh,CAS-Before-RAS Refresh c...

floor Price/Ceiling Price

Part Number:
V53C8258H
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/29

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Product Details

Description



Features:

 256K x 8-bit organization
 EDO Page Mode for a sustained data rateof 71 MHz
 RAS access time: 35, 40, 45, 50 ns
 Low power dissipation
 Read-Modify-Write, RAS-Only Refresh,CAS-Before-RAS Refresh capability
 Refresh Interval: 512 cycles/8 ms
 Available in 24 pin 300 mil Plastic DIP,26/24 pin 300 mil SOJ and 28-pin 300 milTSOP-I packages
 Single 5V±10% Power Supply
 TTL Interface



Pinout

  Connection Diagram




Specifications

Ambient Temperature Under Bias ............................................. 10°C to +80°C
Storage Temperature (plastic) ................................................ 55°C to +125°C
Voltage Relative to VSS ............................................................. 1.0 V to +7.0 V
Data Output Current .................................................................................. 50 mA
Power Dissipation ....................................................................................... 1.0 W



Description

The V53C8258H is a high speed 262,144 x 8 bit CMOS dynamic random access memory. The V53C8258H offers a combination of features: Page Mode with Extended Data Output for high data bandwidth, and Low CMOS standby current.

All inputs and outputs are TTL compatible. Input and output capacitances are significantly lowered to allow increased system performance. Page Mode with Extended Data Output operation allows random access of up to 512 (x8) bits within a row with cycle times as fast as 14 ns. Because of static circuitry, the CAS clock is not in the critical timing path. The flow-through column address latches allow address pipelining while relaxing many critical system timing requirements. The V53C8258H is ideally suited for graphics, digital signal processing and high-performance computing systems.




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