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Part Number: V54C3256164VBUC/T

 

 

 

 

Description: The V54C3256164VBUC/T is a low power four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16. The...


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V54C3256164VBUC/T General Description


The V54C3256164VBUC/T is a low power four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16. The V54C3256164VBUC/T achieves high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock

All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleaved fashion allows random access operation to ccur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is possible depending on burst length, CAS latency and speed grade of the device.

The V54C3256164VBUC/T is ideally suited for high performance, low power systems such as PDA, mobile phone, DSC, and other battery backup applications.

V54C3256164VBUC/T Maximum Ratings

Operating temperature range.....................................................0 to 70 °C
Storage temperature range ..................................................-55 to 150 °C
Input/output voltage.................................................... -0.3 to (VCC+0.3) V
Power supply voltage ............................................................. -0.3 to 4.6 V
Power dissipation ..................................................................................1 W
Data out current (short circuit)............................................................50 mA

V54C3256164VBUC/T Features

4 banks x 4Mbit x 16 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length:
   1, 2, 4, 8 for Sequential Type
   1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 54-Ball SOC BGA/ 54-Pin TSOP II
LVTTL Interface
Single +3.3 V ±0.3 V Power Supply
Low Power Self Refresh Current

V54C3256164VBUC/T Connection Diagram

V54C3256164VBUC/T  Connection Diagram

V54C3256164VBUC/T datasheet

V54C3128
PDF/DataSheet Download

Find V54C3256164VBUC/T Suppliers

  • ·V54C3128164VBGA
  • MOSEL [Mosel Vitelic, Corp] 
  • 128Mbit SDRAM 3.3 VOLT, BGA PACKAGE 
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  • ·V54C3128164VS
  • MOSEL [Mosel Vitelic, Corp] 
  • 128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 
  • 711552 KB
  • V54C3128164VS Datasheet Download
  • ·V54C3128164VT
  • MOSEL [Mosel Vitelic, Corp] 
  • 128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 
  • 711552 KB
  • V54C3128164VT Datasheet Download
  • ·V54C3128404VBGA
  • MOSEL [Mosel Vitelic, Corp] 
  • 128Mbit SDRAM 3.3 VOLT, BGA PACKAGE 
  • 892430 KB
  • V54C3128404VBGA Datasheet Download
  • ·V54C3128404VS
  • MOSEL [Mosel Vitelic, Corp] 
  • 128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 
  • 711552 KB
  • V54C3128404VS Datasheet Download
  • ·V54C3128404VT
  • MOSEL [Mosel Vitelic, Corp] 
  • 128Mbit SDRAM 3.3 VOLT, TSOP II / SOC PACKAGE 8M X 16, 16M X 8, 32M X 4 
  • 711552 KB
  • V54C3128404VT Datasheet Download
  • ·V54C3128804VAT
  • MOSEL [Mosel Vitelic, Corp] 
  • HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 
  • 371182 KB
  • V54C3128804VAT Datasheet Download
  • ·V54C3128804VAT7
  • MOSEL [Mosel Vitelic, Corp] 
  • HIGH PERFORMANCE 143/133/125MHz 3.3 VOLT 16M X 8 SYNCHRONOUS DRAM 4 BANKS X 4Mbit X 8 
  • 371182 KB
  • V54C3128804VAT7 Datasheet Download

V54C3256164VBUC/T Relative Products

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