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Part Number: V54C3128804VAT

 

 

 

 

Description: The V54C3128804VAT is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 8. The V54C3128804VA...


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V54C3128804VAT General Description


The V54C3128804VAT is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 8. The V54C3128804VAT achieves high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock

All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 143 MHz is possible depending on burst length, CAS latency and speed grade of the device.

V54C3128804VAT Maximum Ratings

Operating temperature range...................................................... 0 to 70°C
Storage temperature range ....................................................-55 to 150°C
Input/output voltage..................................................... -0.3 to (VCC+0.3) V
Power supply voltage .............................................................. -0.3 to 4.6 V
Power dissipation ..................................................................................1 W
Data out current (short circuit).............................................................50 mA

V54C3128804VAT Features

4 banks x 4Mbit x 8 organization
High speed data transfer rates up to 143 MHz
Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length:
   1, 2, 4, 8 and Sequential Type
   1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 54 Pin 400 mil TSOP-II
LVTTL Interface
Single +3.3 V±0.3 V Power Supply

V54C3128804VAT Connection Diagram

V54C3128804VAT  Connection Diagram

V54C3128804VAT datasheet

V54C3128804VAT
PDF/DataSheet Download

  • Datasheet: V54C3128804VAT
  • File Size: 371182 KB
  • Manufacturer: MOSEL [Mosel Vitelic, Corp]
  • Click here to Download

Find V54C3128804VAT Suppliers

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  • ·V54C3128404VT
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  • MOSEL [Mosel Vitelic, Corp] 
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