W332M64V-XBX

Features: · High Frequency = 100, 125, 133MHz· Package:219 Plastic Ball Grid Array (PBGA), 25 x 25mm· 3.3V± 0.3V power suppl· Fully Synchronous; all signals registered on pos i tive edge of system clock cycle· Internal pipelined operation; column address can be changed every clock cycle· Internal ...

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SeekIC No. : 004544599 Detail

W332M64V-XBX: Features: · High Frequency = 100, 125, 133MHz· Package:219 Plastic Ball Grid Array (PBGA), 25 x 25mm· 3.3V± 0.3V power suppl· Fully Synchronous; all signals registered on pos i tive edge of system c...

floor Price/Ceiling Price

Part Number:
W332M64V-XBX
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

· High Frequency = 100, 125, 133MHz
· Package:
219 Plastic Ball Grid Array (PBGA), 25 x 25mm
· 3.3V± 0.3V power suppl
· Fully Synchronous; all signals registered on pos i tive
edge of system clock cycle
· Internal pipelined operation; column address can be
changed every clock cycle
· Internal banks for hiding row access/precharge
· Programmable Burst length 1,2,4,8 or full page
· 8192 refresh cycles
· Commercial, Industrial and Military Temperature
Ranges
· Organized as 32M x 64
· Weight: W332M64V-XBX - 2.5 grams typical





Specifications

Parameter Unit
Voltage on VCC , VCCQ Supply relative to Vss
-1 to 4.6 V
Voltage on NC or I/O pins relative to Vss -1 to 4.6 V
Operating Temperature TA (Mil) -55 to +125
Operating Temperature TA (Ind) -40 to +85
Storage Temperature, Plastic -55 to +125
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings"
may cause per ma nent damage to the device. This is a stress rating only and
func tion al op er a tion of the device at these or any other conditions greater
than those in di cat ed in the operational sections of this speci cation is not
implied. Exposure to ab so lute maximum rating con di tions for extended
periods may affect reliability.





Description

The 256MByte (2Gb) SDRAM W332M64V-XBX is a high-speed CMOS,dy nam ic ran dom-access, memory using 4 chips ontaining ,870,912 bits. Each chip is internally con gured as a quad-bank DRAM with a syn chro nous interface. Each of the chips ,217,728-bit banks is orga nized as 8,192 rows by 1,024 columns by 16 bits.

Read and write accesses to the SDRAM W332M64V-XBX are burst oriented; ac cess es start at a selected location and continue for a pro grammed number of locations in a programmed se quence. Ac cess es be gin with the registration of an ACTIVE com nd, which is then fol lowed by a READ or WRITE com mand. The address bits reg is tered coincident with the AC TIVE mand are used to select the bank and row to be accessed (BA0, BA1 select the bank; A012 select the row). The address bits reg is tered co in ci dent with the READ or WRITE com mand are used to se lect the starting col umn lo ca tion for the rst ac cess.

The SDRAM W332M64V-XBX provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a rst terminate option. An AUTO PRECHARGE function may be en abled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

The 2Gb SDRAM W332M64V-XBX uses an internal pipelined architecture to achieve high-speed operation. This architecture is com pat i le with the 2n rule of prefetch architectures, but it also allows the column ad dress to be changed on every clock cycle to e a high-speed, fully random access. Precharging one bank while ac cess ing one of the other three banks will hide the e cycles and provide seam less, highspeed, random-access op er a tion.






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