W3E32M72S-XBX

NOTE:Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage to the device. This is a stress rating only and func tion al op er a tion of the device at these or any other conditions greater than those in di cat ed in the operational sections of this speci cation is not implied. Exposure to ab so lute maximum rating con di tions for extended periods may affect reliability.

The 256MByte (2Gb) DDR SDRAM W3E32M72S-XBX  is a high-speed CMOS, dy nam ic ran dom-access, memory using 5 chips containing
536,870,912 bits. Each chip is internally configured as a quad-bank DRAM.

The 256MB DDR SDRAM W3E32M72S-XBX uses a double data rate ar chi tec ture to achieve high-speed operation. The double data rate ar chi tec ture is essentially a 2n-prefetch architecture with an in ter face designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data tansfer at the internal DRAM core and two cor re spond ing n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

A bi-directional data strobe (DQS) W3E32M72S-XBX  is transmitted externally, along with data, for use in data capture at the receiver.strobe transmitted by the DDR SDRAM during READs and by the memory contoller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte.

The 256MB DDR SDRAM W3E32M72S-XBX operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com mands (ad dress and control signals) are registered at every positive edge of CK. Input data is registered on both edg es of DQS, and out put data is ref er enced to both edges of DQS, as well as to both edges of CK.