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W530

Features: • Cypress PREMIS™ family offering• Generates an EMI optimized clocking signal at the output• Selectable output frequency range• Single 1.25%, 2.5%, 5% or 10% down or center spread output• Integrated loop filter components• Operates with a 3.3 or ...

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W530: Features: • Cypress PREMIS™ family offering• Generates an EMI optimized clocking signal at the output• Selectable output frequency range• Single 1.25%, 2.5%, 5% or 10% ...

W530 Data Sheet

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Part Number:
W530
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the output
• Selectable output frequency range
• Single 1.25%, 2.5%, 5% or 10% down or center spread output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 20-pin SSOP (Small Shrunk Outline Package)


Pinout

Connection Diagram


Specifications

Supply Voltages: ....................................... VDD = 3.3V±0.3V
                                                                  or VDD = 5V±10%
Frequency range: ..........................13 MHz Fin 120 MHz
Cycle to Cycle Jitter: .........................................250 ps (max)
Output duty cycle: .............................. 40/60% (worst case)


Description

The W530 product is one of a series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign.

In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation.




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