W90210F

Features: Main features of the W90210F· PA-RISC architecturePA-RISC 1.1 third edition instruction setPA-RISC level zero implementationSupport PA-RISC Multimedia Extension 1.0 instruction setW90K binary compatible for user software· High-performance implementationFive-stage pipelinePrecise, efficie...

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SeekIC No. : 004545253 Detail

W90210F: Features: Main features of the W90210F· PA-RISC architecturePA-RISC 1.1 third edition instruction setPA-RISC level zero implementationSupport PA-RISC Multimedia Extension 1.0 instruction setW90K bin...

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Part Number:
W90210F
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/24

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Product Details

Description



Features:

Main features of the W90210F
· PA-RISC architecture
PA-RISC 1.1 third edition instruction set
PA-RISC level zero implementation
Support PA-RISC Multimedia Extension 1.0 instruction set
W90K binary compatible for user software
· High-performance implementation
Five-stage pipeline
Precise, efficient handling of pipeline stalls and exceptions
Delayed branch with static branch prediction
Forward: not taken
Backward: taken
One-cycle stall when prediction is wrong
HIT under miss
Both load and store can be queued when miss
Load/store single cycle execution after previous miss
· On-chip cache memory
Internal I-cache: Direct mapped, 4 KB cache (256 entries, four words/entry)
Wrap around fetching when cache miss
Cache freeze capability
Internal D-cache: 2-way set associative, 2 KB cache ´(264 entries, four words/entry)
Write-back cache with write buffer
Write-through option
New line send to CPU before dirty line write back
· Enhanced debug capability
Debug SFU supports both instruction breakpoints and data breakpoints
· High on-chip integration and simple I/O interface
486-like bus interface for CPU core
Memory controller to support four banks of DRAM and ROM/FLASH ROM
2-channel 8-bit DMA controller
PCI bridge
Two Serial ports with FIFO
Extended Capabilities Port (ECP)
Two 24-bit timer/counters
· Power Down mode
Provide power down mode for power saving operation



Pinout

  Connection Diagram


Description

The W90210F Embedded Controller is part of Winbond¢s W90K Embedded processor family. The processor is a high-performance, highly integrated 32-bit processor intended for a wide range of embedded applications, such as
set-top box, web browser, X-terminal, and visual/data communication devices..

The W90210F CPU core is based on the HP PA-RISC architecture and is upward code compatible with the W90K. The PA-RISC architecture incorporates traditional RISC elements, such as instruction pipelining, a register- oregister
instruction set and a large, general-purpose register file. Separate on-chip instruction and data caches allow the W90210F to fetch an instruction and access data in a single processor cycle.

The W90210F includes several features that greatly increase performance, reduce system component count and ease the overall system design task. In addition to its cache memories, the W90210F¢s on-chip support features  include a DRAM controller, ROM/FLASH ROM interface, PCI bridge, DMA controller, two serial ports with FIFO, IEEE 1284 parallel port, timer/counters, and enhanced debug support- all features that are commonly required in embedded
applications.




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