W941232AD

W941232AD is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 1,048,576 words * 4 banks * 32 bits. Using pipelined architecture and 0.175 m process technology, W941232AD delivers a data bandwidth of up to 800M words per second (-5). For different application, W941232AD was sorted into the following speed grades: -5. The -5 parts can run up to 200 MHz/CL3.

All inputs of W941232AD reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe).

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W941232AD is ideal for main memory in high performance applications.