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W942516AH

Features: · 2.5V ± 0.2V Power Supply· Up to 143 MHz Clock Frequency· Double Data Rate architecture; two data transfers per clock cycle· Differential clock inputs (CLK andCLK )· DQS is edge-aligned with data for Read; center-aligned with data for Write· CAS Latency: 2 and 2.5· Burst Length: 2, 4, a...

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SeekIC No. : 004545333 Detail

W942516AH: Features: · 2.5V ± 0.2V Power Supply· Up to 143 MHz Clock Frequency· Double Data Rate architecture; two data transfers per clock cycle· Differential clock inputs (CLK andCLK )· DQS is edge-aligned w...

W942516AH Data Sheet

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Part Number:
W942516AH
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/22

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Product Details

Description



Features:

· 2.5V ± 0.2V Power Supply
· Up to 143 MHz Clock Frequency
· Double Data Rate architecture; two data transfers per clock cycle
· Differential clock inputs (CLK and CLK )
· DQS is edge-aligned with data for Read; center-aligned with data for Write
· CAS Latency: 2 and 2.5
· Burst Length: 2, 4, and 8
· Auto Refresh and Self Refresh
· Precharged Power Down and Active Power-Down
· Write Data Mask
· Write Latency = 1
· 8K Refresh cycles / 64 mS
· Interface: SSTL-2
· Packaged: TSOP II 66 pin, 400 x 875mil , 0.65mm pin pitch


Pinout

Connection Diagram


Specifications

PARAMETER SYMBOL RATING UNIT NOTES
Input, Output Voltage VIN, VOUT -0.3 ~ VDDQ +0.3 V 1
Power Supply Voltage VDD, VDDQ -0.3 ~ 3.6 V 1
Operating Temperature TOPR 0 ~ 70   1
Storage Temperature TSTG -55 ~ 150   1
Soldering Temperature (10s) TSOLDER 260   1
Power Dissipation PD 1 W 1
Short Circuit Output Current IOUT 50 mA 1



Description

W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words ´ 4 banks ´ 16 bits. Using pipelined architecture and 0.175 mm process technology, W942516AH delivers a data bandwidth of up to 286M words per second (-7). To fully comply with the personal computer industrial standard, W942516AH is sorted into three speed grades: -7, -75 and -8. The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the - 75 is compliant to the DDR266/CL2.5 specification, the -8 is compliant to the DDR200/CL2 specification

All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. And Write and Read data of W942516AH are synschronized with the both edges of DQS (Data Strobe).

By having a programmable Mode Register, the system of W942516AH can change burst length, latency cycle, interleave or sequential burst to m




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