W942516CH

Features: • 2.5V ±0.2V Power Supply for DDR266• 2.5V ±0.2V Power Supply for DDR333• 2.6V ±0.1V Power Supply for DDR400• Up to 200 MHz Clock Frequency• Double Data Rate architecture; two data transfers per clock cycle• Differential clock inputs (CLK and CLK)̶...

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W942516CH Picture
SeekIC No. : 004545335 Detail

W942516CH: Features: • 2.5V ±0.2V Power Supply for DDR266• 2.5V ±0.2V Power Supply for DDR333• 2.6V ±0.1V Power Supply for DDR400• Up to 200 MHz Clock Frequency• Double Data Rate ...

floor Price/Ceiling Price

Part Number:
W942516CH
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

• 2.5V ±0.2V Power Supply for DDR266
• 2.5V ±0.2V Power Supply for DDR333
• 2.6V ±0.1V Power Supply for DDR400
• Up to 200 MHz Clock Frequency
• Double Data Rate architecture; two data transfers per clock cycle
• Differential clock inputs (CLK and CLK)
• DQS is edge-aligned with data for Read; center-aligned with data for Write
• CAS Latency: 2, 2.5 and 3
• Burst Length: 2, 4 and 8
• Auto Refresh and Self Refresh
• Precharged Power Down and Active Power Down
• Write Data Mask
• Write Latency = 1
• 8K Refresh Cycles / 64 mS
• Interface: SSTL-2
• Packaged in TSOP II 66-pin, 400 x 875 mil, 0.65 mm pin pitch}



Pinout

  Connection Diagram


Specifications

PARAMETER
SYMBOL
RATING
UNIT
Input/Output Voltage
VIN, VOUT
0.3 − VDDQ +0.3
V
Power Supply Voltage
VDD, VDDQ
-0.3 − 3.6
V
Operating Temperature
TOPR
0 − 70
°C
Storage Temperature
TSTG
-55 − 150
°C
Soldering Temperature (10s)
TSOLDER
260
°C
Power Dissipation
PD
1
W
Short Circuit Output Current
IOUT
50
mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.


Description

W942516CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words * 4 banks * 16 bits. Using pipelined architecture and 0.13 m process technology, W942516CH delivers a data bandwidth of up to 400M words per second (-5). To fully comply with the personal computer industrial standard, W942516CH is sorted into four speed grades: -5, -6, -7, -75 The -5 is compliant to the 200 MHz/CL2.5 & CL3 specification, The -6 is compliant to the 166 MHz/CL2.5 specification, the -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -75 is compliant to the DDR266/CL2.5 specification.

All Inputs of W942516CH reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference point for the differential clock is when the CLK and CLKsignals cross during a transition. And Write and Read data are synschronized with the both edges of DQS (Data Strobe).

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W942516CH is ideal for main memory in high performance applications.




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