WED2DL32512V

The WED2DL32512V employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process. WEDC's 16Mb SyncBurst SRAMs integrate two 512K x 16 SRAMs into a single BGA package to provide 512K x 32 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs of WED2DL32512V include all addresses, all data inputs, active LOW chip enable (CE), burst control input (ADSC) and byte write enables (BW0-3). Asynchronous inputs include the output enable (OE), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. Write cycles can be from one to four bytes wide, as controlled by the write control inputs. Burst operation can be initiated with the address status controller (ADSC) input.