WED2CG472512V-D2

The WED2CG472512V is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72. The Module contains sixteeen (16) Synchronous Burst RAM devices, packaged in the industry standard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The Module Architecture WED2CG472512V is defined as a Sync/SyncBurst, Flow- Through, with support for either linear or sequential burst. This Module provides high performance, 2-1-1-1 accesses when used in Burst Mode, and when used in Synchronous Only Mode, WED2CG472512V provides a high performance cost advantage over BiCMOS asynchronous device architectures.

Synchronous Only operations WED2CG472512V are performed via strapping ADSC Low, and ADSP/ADV High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes.

Synchronous/Synchronous Burst WED2CG472512V operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output Enable. This Module WED2CG472512V has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as Quad Words in both Read and Write Operations.