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WV3EG264M64EFSU

Features: · PC2700 @ CL2.5· Double-data-rate architecture· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2.5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (sequential & interleave)· Auto and self refresh, (8K/64ms...

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SeekIC No. : 004546957 Detail

WV3EG264M64EFSU: Features: · PC2700 @ CL2.5· Double-data-rate architecture· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2.5 (clock)· Programmable Burst Le...

WV3EG264M64EFSU Data Sheet

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Part Number:
WV3EG264M64EFSU
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/17

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Product Details

Description



Features:

· PC2700 @ CL2.5
· Double-data-rate architecture
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2.5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Auto and self refresh, (8K/64ms refresh)
· Serial presence detect
· Power supply: VCC/VCCQ: 2.5V ± 0.2V
· Dual Rank
· Standard 200 pin SO-DIMM package


Specifications

Symbol
Parameter
Rating
 Units
VIN, VOUT
Voltage on any pin relative to VSS
-0.5 to 3.3
V
VCC
Voltage on VCC supply relative to VSS
-1.0 to 3.6
V
VCCQ
Voltage on VCCQ supply relative to VSS
-1.0 to 3.6
V
TSTG
Storage Temperature
-55 to +150
°C
TA
Operating Temperature
0 to +70
°C
PD
Power Dissipation
16
W
IOS
Short Circuit Current
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The WV3EG264M64EFSU is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen 64Mx8 bit with 4 banks DDR SDRAMs in FBGA packages mounted on a 200 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions.




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