WV3EG64M72ETSU-D3

`Double-data-rate architecture
`PC2700 @CL 2.5
`Bi-directional data strobes (DQS)
`Differential clock inputs (CK & CK#)
`Programmable Read Latency 2,2.5 (clock)
`Programmable Burst Length (2,4,8)
`Programmable Burst type (sequential & interleave) 
`Edge aligned data output, center aligned data input. 
`Auto and self refresh, (8K/64ms refresh)
`Serial presence detect with EEPROM
`Power supply: 
  V<sub>CC</sub>  = V<sub>CCQ</sub>  = +2.5V 0.2  
`184 pin DIMM package 
 D3 PCB height:  28.58mm (1.125")

The WV3EG64M72ETSU-D3 is a 64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component s. The module consists of nine 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on bot h edges and Burst Lengths allow the WV3EG64M72ETSU-D3 to be useful for a variety of high bandwidth, high performance memory system applications.