XC2S100

Features: • Second generation ASIC replacement technology- Densities as high as 5,292 logic cells with up to 200,000 system gates- Streamlined features based on Virtex architecture- Unlimited reprogrammability- Very low cost• System level features- SelectRAM+™ hierarchical memory...

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SeekIC No. : 004547799 Detail

XC2S100: Features: • Second generation ASIC replacement technology- Densities as high as 5,292 logic cells with up to 200,000 system gates- Streamlined features based on Virtex architecture- Unlimited ...

floor Price/Ceiling Price

Part Number:
XC2S100
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2021/1/21

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Product Details

Description



Features:

• Second generation ASIC replacement technology
- Densities as high as 5,292 logic cells with up to 200,000 system gates
- Streamlined features based on Virtex architecture
- Unlimited reprogrammability
- Very low cost
• System level features
- SelectRAM+™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K bit block RAM
· Fast interfaces to external RAM
- Fully PCI compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging
- Low cost packages available in all densities
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Hot swap Compact PCI friendly
- Zero hold time simplifies system timing
• Fully supported by powerful Xilinx development system
- Foundation ISE Series: Fully integrated software
- Alliance Series: For use with third-party tools
- Fully automatic mapping, placement, and routing



Description

The Spartan™-II 2.5V Field-Programmable Gate Array family XC2S100 gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The six-member family offers densities ranging from 15,000 to 200,000 system gates, as shown in Table 1. System performance is supported up to 200 MHz.

Spartan-II devices XC2S100 deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined Virtex-based architecture.Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements.

The Spartan-II family XC2S100 is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost,lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).




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