XC2S100E-6TQ144C

Mounting Type: Surface Mount
Operating Temperature: 0°C ~ 85°C
Package / Case: 144-LQFP
Supplier Device Package: 144-TQFP (20x20)
Number of I /O: 102
Total RAM Bits: 40960
Manufacturer: Xilinx Inc
Number of Gates: 100000
Number of LABs/CLBs: 600
Number of Logic Elements/Cells: 2700
Voltage - Supply: 1.71 V ~ 1.89 V
Series: Spartan®-IIE


Features:

• Second generation ASIC replacement technology
- Densities as high as 6,912 logic cells with up to 300,000 system gates
- Streamlined features based on Virtex-E architecture
- Unlimited in-system reprogrammability
- Very low cost
• System level features
- SelectRAM+™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K-bit true dual-port block RAM
· Fast interfaces to external RAM
- Fully 3.3V PCI compliant to 64 bits at 66 MHz and CardBus compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging
- Low cost packages available in all densities
- Family footprint compatibility in common packages
- 19 high-performance interface standards, including LVDS and LVPECL
- Up to 120 differential I/O pairs that can be input, output, or bidirectional
- Zero hold time simplifies system timing
• Fully supported by powerful Xilinx ISE development system
- Fully automatic mapping, placement, and routing
- Integrated with design entry and verification tools


Description

The Spartan™-IIE 1.8V Field-Programmable Gate Array family XC2S100E-6TQ144C gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The five-member family offers densities ranging from 50,000 to 300,000 system gates, as shown in Table 1.

System performance XC2S100E-6TQ144C is supported beyond 200 MHz. Spartan-IIE devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined architecture based on the proven Virtex™-E platform. Features include block RAM (to 64K bits), distributed RAM (to 98,304 bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loops). Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The Spartan-IIE family is a superior alternative to mask-programmed ASICs.

The FPGA XC2S100E-6TQ144C avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs).