XCF16P

Features: • In-System Programmable PROMs for Configuration of Xilinx FPGAs• Low-Power Advanced CMOS FLASH Process• Endurance of 20,000 Program/Erase Cycles• Operation over Full Industrial Temperature Range (40 to +85)• Available in small footprint packages: VO20, VO48...

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SeekIC No. : 004548106 Detail

XCF16P: Features: • In-System Programmable PROMs for Configuration of Xilinx FPGAs• Low-Power Advanced CMOS FLASH Process• Endurance of 20,000 Program/Erase Cycles• Operation over Fu...

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Part Number:
XCF16P
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2018/9/22

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Product Details

Description



Features:

• In-System Programmable PROMs for Configuration of Xilinx FPGAs
• Low-Power Advanced CMOS FLASH Process
• Endurance of 20,000 Program/Erase Cycles
• Operation over Full Industrial Temperature Range (40 to +85)
• Available in small footprint packages: VO20, VO48, and FS48
• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
• JTAG Command Initiation of Standard FPGA Configuration
• Cascadable for Storing Longer or Multiple Bitstreams
• Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
• I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V
• Design Support Using the Xilinx Alliance ISE and Foundation ISE Series Software Packages
• XCF01S/XCF02S/XCF04S
- 3.3V supply voltage
- Serial FPGA configuration interface
• XCF08P/XCF16P/XCF32P
- 1.8V supply voltage
- Serial or parallel FPGA configuration interface
- Design revision technology enables storing and accessing multiple design revisions for configuration
- Built-in data decompressor compatible with Xilinx advanced compression technology



Pinout

  Connection Diagram


Specifications

Symbol Description XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
Units
VCCINT Internal supply voltage relative to GND 0.5 to +4.0 0.5 to +2.7 V
VCCO I/O supply voltage relative to GND 0.5 to +4.0 0.5 to +4.0 V
VCCJ JTAG I/O supply voltage relative to GND 0.5 to +4.0 0.5 to +4.0 V
VIN Input voltage with respect to GND VCCO < 2.5V 0.5 to +3.6 0.5 to VCCO+0.5 V
VCCO 2.5V 0.5 to +5.5 0.5 to VCCO+0.5 V
VTS Voltage applied to High-Z output VCCO < 2.5V 0.5 to +3.6 0.5 to VCCO+0.5 V
VCCO 2.5V 0.5 to +5.5 0.5 to VCCO+0.5 V
TSTG Storage temperature (ambient) 65 to +150 65 to +150
TSOL
(3)
Maximum soldering temperature (10s @ 1/16 in.) +220 +220
TJ Junction temperature +125 +125

Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins can undershoot to 2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA.
2. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
3. For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com.




Description

Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Megabit (Mbit) densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that support Master Serial and Slave Serial FPGA configuration modes (Figure 1). The XCFxxP version includes 32-Mbit, 16-Mbit, and 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 2). A summary of the Platform Flash PROM family members and supported features is shown in Table 1.




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