Features: RECEIVER
` On chip Clock and Data Recovery circuit for high input jitter tolerance
` Meets E3/DS3/STS-1 Jitter Tolerance Requirement
` Detects and Clears LOS as per G.775
` Receiver Monitor mode handles up to 20 dB flat loss with 6 dB cable attenuation
` On chip B3ZS/HDB3 encoder and decoder that can be either enabled or disabled
` On-chip clock synthesizer provides the appropriate rate clock from a single 12.288 MHz Clock
` Provides low jitter output clock
TRANSMITTER
` Compliant with Bellcore GR-499, GR-253 and ANSI T1.102 Specification for transmit pulse
` Tri-state Transmit output capability for redundancy applications
` Each Transmitter can be turned on or off CONTROL AND DIAGNOSTICS
` Parallel Microprocessor Interface for control and configuration
` Supports optional internal Transmit driver monitoring
` Each channel supports Analog, Remote and Digital Loop-backs
` Single 3.3 V ± 5% power supply
` 5 V Tolerant digital inputs
` Available in 217 pin BGA Package
` - 40 to 85 Industrial Temperature Range
TRANSMIT INTERFACE CHARACTERISTICS
` Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the line
` Integrated Pulse Shaping Circuit
` Built-in B3ZS/HDB3 Encoder (which can be disabled)
` Accepts Transmit Clock with duty cycle of 30%- 70%
` Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications
` Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and ANSI T1.102_1993
` Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253- CORE
` Transmitter can be turned off in order to support redundancy designs
RECEIVE INTERFACE CHARACTERISTICS
` Integrated Adaptive Receive Equalization (optional) for optimal Clock and Data Recovery
` Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications
` Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications
` Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications
` Declares Loss of Lock (LOL) Alarm
` Built-in B3ZS/HDB3 Decoder (which can be disabled)
` Recovered Data can be muted while the LOS Condition is declared
` Outputs either Single-Rail or Dual-Rail data to the Terminal EquipmentApplication· E3/DS3 Access Equipment
· DSLAMs
· Digital Cross Connect Systems
· CSU/DSU Equipment
· Routers
· Fiber Optic TerminalsPinout
Specifications
| No. ofCH |
6 |
| DataRate(s) |
DS3, E3, STS-1 |
| Clk Rec |
Yes |
| SH/LH |
n/a |
| Temp.Range |
Ind. |
| OpPwr Sup/Max Cur |
3V |
| Pkgs |
BGA-217 |
| SYMBOL |
PARAMETER |
MIN |
MAX |
UNITS |
COMMENTS |
| VDD |
Supply Voltage |
-0.5 |
6.0 |
V |
Note 1 |
| VIN |
Input Voltage at any Pin |
-0.5 |
5.5 |
V |
Note 1 |
| IIN |
Input current at any pin |
|
100 |
mA |
Note 1 |
| STEMP |
Storage Temperature |
-65 |
150 |
|
Note 1 |
| ATEMP |
Ambient Operating Temperature |
-40 |
85 |
|
linear air flow 0ft/min |
| ThetaJA |
Thermal Resistance |
|
23 |
/W |
linear air flow 0ft/min |
| MLEVL |
Exposure to Moisture |
5 |
|
level |
EIA/JEDEC
JESD22-A112-A |
| ESD |
ESD Rating |
2000 |
|
V |
Note 2 |
NOTES:
1. Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair
reliability of the device.
2. ESD testing method is per MIL-STD-883D,M-3015.7
3. With Linear Air flow of 200 ft/min, reduce Theta JA by 20%, Theta JC is unchanged.Description
The XRT73L06 is a Six-Channel fully integrated Line Interface Unit (LIU) for E3/DS3/STS-1 applications. It incorporates six independent Receivers and Transmitters in a single 208-pin QFP package.
Each channel of the XRT73L06 can be configured to operate in E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz) rates that are independent of each other. Each transmitter can be turned off and tri-stated for redundancy support and power conservation.
The XRT73L06's differential receivers provide high noise interference margin and are able to receive the data over 1000 feet of cable, or with up to 12 dB of cable attenuation.
The XRT73L06 provides a Parallel Microprocessor Interface for programming and control. The XRT73L06 supports local, remote and digital loop-backs. The XRT73L06 also contains an on-board Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error.
The XRT73L06 is a six channel fully integrated Line Interface Unit (LIU) for E3/DS3/STS-1 applications. The LIU incorporates 6 independent Receivers and Transmitters in a single 217 Lead BGA package. Each channel of the XRT73L06 can be independently configured to operate in E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz). Each transmitter can be turned off and tri-stated for redundancy support or for conserving power.
The XRT73L06's differential receiver provides high noise interference margin and is able to receive data over 1000 feet of cable or with up to 12 dB of cable attenuation.
The XRT73L06 provides a Parallel Microprocessor Interface for programming and control.
The XRT73L06 supports analog, remote and digital loop-backs. The device also has a built-in Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error for diagnostic purposes.
XRT73L06 Data Sheet
