Specifications
| No. ofCH |
1 |
| DataRate(s) |
T1/E1/J1 |
| Clk Rec |
Yes |
| SH/LH |
S/L |
| Temp.Range |
Ind. |
| OpPwr Sup/Max Cur |
1.8V/3.3V |
| Pkgs |
LQFP-128, LQFP-80 |
Description
The XRT86VL30 is a single channel T1/E1/J1 BITS clock recovery element and framer and LIU integrated solution featuring R3 technology (Relayless, Reconfigurable, Redundancy). The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL30 provides protection from power failures and hot swapping.
The XRT86VL30 contains an integrated DS1/E1/J1 framer and LIU which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. The framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats.
The Framer block contains XRT86VL30's own Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC controllers which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers which extract the payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and write the contents into the Receive HDLC buffers. The framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound T1/E1/J1 frames.
The XRT86VL30 fully meets all of the latest T1/E1/J1 specifications: ANSI T1.101-1999, ANSI T1/E1.107-1988, ANSI T1/E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703 (Including Section 13 - Synchronization), G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921.
XRT86VL30 Data Sheet
