XRT86VL3x

•Independent, full duplex DS1 Tx and Rx Framer/LIUs
•Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz  synchronous back plane connections with jitter and wander attenuation
•Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
•Programmable output clocks for Fractional T1/E1/J1
•Supports Channel Associated Signaling (CAS)
•Supports Common Channel Signalling (CCS)
•Supports ISDN Primary Rate Interface (ISDN PRI) signaling
•Extracts and inserts robbed bit signaling (RBS)
•3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte buffers  buffer 0 / buffer 1)
•HDLC Controllers Support SS7
•Timeslot assignable HDLC
•V5.1 or V5.2 Interface
•Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface every 1 second or for a single transmission
•Alarm Indication Signal with Customer Installation signature (AIS-CI)
•Remote Alarm Indication with Customer Installation (RAI-CI)
•Gapped Clock interface mode for Transmit and Receive.
•Intel/Motorola and Power PC interfaces for configuration, control and status monitoring
•Parallel search algorithm for fast frame synchronization
•Wide choice of T1 framing structures: SF/D4, ESF, SLC®96, T1DM and N-Frame (non-signaling)
•Direct access to D and E channels for fast transmission of data link information
•PRBS, QRSS, and Network Loop Code generation and detection
•Programmable Interrupt output pin
•Supports programmed I/O and DMA modes of Read-Write access
•Each framer block encodes and decodes the T1/E1/J1 Frame serial data
•Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms
•Detects OOF, LOF, LOS errors and COFA conditions
•Loopbacks: Local (LLB) and Line remote (LB)
•Facilitates Inverse Multiplexing for ATM
•Performance monitor with one second polling
•Boundary scan (IEEE 1149.1) JTAG test port
•Accepts external 8kHz Sync reference
•1.8V Inner Core Voltage
•3.3V I/O operation with 5V tolerant inputs

The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3  echnology (Relayless, Reconfigurable, Redundancy) that comes in a 2-channel, 4-channel, or 8-channel package. The physical  nterface is optimized with internal impedance, and with the patented pad structure, the XRT86VL3x provides  rotection from power failures and hot swapping.

The XRT86VL3x contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error  ccumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and  ransmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be  onfigured to frame to the common DS1/E1/J1 signal formats.

Each Framer block contains its own Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC  ontrollers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There  re 3 Receive HDLC controllers per channel which extract the payload content of Receive LAPD Message frames from  he incoming T1/E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a  ransmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound  1/E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access  o the Data Link bits of the inbound T1/E1/J1 frames.

The XRT86VL3x fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733,  T&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic unctions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation,  erformance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload  rocessing according to ITU-T standard Q.921.