Z16C30

• Two Independent 0-to-10-mbps Full-Duplex Channels, each with Two Baud Rate Generators and One Digital Phase-Locked Loop for Clock Recovery
• 32-Byte Data FIFO's for each Receiver and Transmitter
• 110-ns Bus Cycle Time, 16-Bit Data Bus Bandwidth
• Multi-Protocol Operation under Program Control with Independent Mode Selection for Receiver and Transmitter
• Async Mode with 1 to 8 Bits/Character, 1/16 to 2 Stop Bits/Character in 1/16-Bit Increments; Programmable Clock Factor; Break Detect and Generation; Odd, Even, Mark, Space or no Parity and Framing Error Detection; Supports One Address/Data Bit and MIL STD 1553B Protocols
• Byte Oriented Synchronous Mode with One to Eight Bits/Character; Programmable Idle Line Condition; Optional Receive Sync Stripping; Optional Preamble Transmission; 16- or 32-Bit CRC and Transmit-to-Receive Slaving (for X.21)
• Bisync Mode with 2- to 16-Bit Programmable Sync Character; Programmable Idle Line Condition; Optional Receive Sync Stripping; Optional Preamble Transmission; 16- or 32-Bit CRC
• Transparent Bisync Mode with EBCDIC or ASCII Character Code; Automatic CRC Handling; Programmable Idle Line Condition; Optional Preamble Transmission; Automatic Recognition of DLE, SYN, SOH, ITX, ETX, ETB, EOT, ENQ and ITB
• External Character Sync Mode for Receive
• HDLC/SDLC Mode with Eight-Bit Address Compare; Extended Address Field Option; 16- or 32-Bit CRC; Programmable Idle Line Condition; Optional Preamble Transmission and Loop Mode
• DMA Interface with Separate Request and Acknowledge for Each Receiver and Transmitter
• Channel Load Command for DMA Controlled Initialization
• Flexible Bus Interface for Direct Connection to Most Microprocessors; User Programmable for 8 or 16 Bits Wide. Directly Supports 680X0 Family or 8X86 Family Bus Interfaces
• Low Power CMOS
• 68-Pin PLCC/100-Pin VQFP Packages

The Z16C30 USC™ Universal Serial Controller is a dualchannel multi-protocol data communications peripheral designed for use with any conventional multiplexed or nonmultiplexed bus. The USC functions as a serial-to-parallel, parallel-to-serial converter/controller and may be software configured to satisfy a wide variety of serial communications applications. The device contains a variety of new, sophisticated internal functions including two baud rate generators per channel, one digital phase-locked loop per channel, character counters for both receive and transmit in each channel and 32-byte data FIFO's for each receiver and transmitter (Figure 1).

ZiLOG now offers a high speed version of the USC with improved bus bandwidth. CPU bus accesses have been shortened from 160 ns per access to 110 ns per access. The USC has a transmit and receive clock range of up to 10 MHz