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ZL30110

Features: • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz• Provides a range of output clocks:• 65.536 MHz TDM clock locked to the input reference• General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator• General purpose 125...

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SeekIC No. : 004550948 Detail

ZL30110: Features: • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz• Provides a range of output clocks:• 65.536 MHz TDM clock locked to the input reference• General purpose...

ZL30110 Data Sheet

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Part Number:
ZL30110
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
• Provides a range of output clocks:
• 65.536 MHz TDM clock locked to the input reference
• General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator
• General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator
• Provides DPLL lock and reference fail indication
• Automatic free run mode on reference fail
• DPLL bandwidth of 922 Hz for all rates of inputreference and 58 Hz for an 8 kHz input reference
• Less than 5 psecrms on 25 MHz outputs, and less than 0.6 nspp intrinsic jitter on the all other outputs
• Minimal input to output and output to output skew
• 25 MHz external master clock source: clock oscillator or crystal
• Simple hardware control interface


Application

• Clock rate conversion PLL for Telecommunication Equipment
• Small/Medium Enterprise Router / Gateway
• Broadband access (xPON/xDSL) CPE gateway


Pinout

Connection Diagram


Specifications

  Parameter Symbol Min. Max. Units
1 Supply voltage VDD_R -0.5 4.6 V
2 Core supply voltage VCORE_R -0.5 2.5 V
3 Voltage on any digital pin VPIN -0.5 6 V
4 Voltage on OSCi and OSCo pin VOSC -0.3 VDD+0.3 V
5 Current on any pin IPIN   30 mA
6 Storage temperature TST -55 125
7 ESD rating VESD   K V

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated.


Description

The ZL30110 clock rate conversion digital phaselockedloop (DPLL) provides accurate and reliable frequency conversion.

The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator.

In the locked mode, the reference input of ZL30110 is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.




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