Position: Home  > All Categories> Integrated Circuits (ICs) > ZL30121

ZL30121

Features: • Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks• Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 3 ps...

product image

ZL30121 Picture
See larger image
SeekIC No. : 004550953 Detail

ZL30121: Features: • Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks...

ZL30121 Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
ZL30121
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/4/25

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and 
   the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks
• Internal APLL provides standard output clock frequencies up to 622.08 MHz with jitter < 3 ps RMS suitable for
  GR-253-CORE OC-12 and G.813 STM-16 interfaces
• Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz
   in addition to 2 kHz
• Provides two DPLLs which are independently configurable through a serial software interface
• DPLL1 provides all the features necessary for generating SONET/SDH compliant clocks including automatic
   hitless reference switching, automatic mode selection (locked, free-run, holdover), selectable loop bandwidth
   and pull-in range
• DPLL2 provides a comprehensive set of features necessary for generating derived output clocks and other
  general purpose clocks
• Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in
  addition to 2 kHz
• Supports master/slave configuration for AdvancedTCATM
• Configurable input to output delay and output to output phase alignment
• Optional external feedback path provides dynamic input to output delay compensation
• Provides 3 sync inputs for output frame pulse alignment
• Generates several styles of output frame pulses with selectable pulse width, polarity and frequency
• Flexible input reference monitoring automatically disqualifies references based on frequency and
   phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan



Application

• AdvancedTCATM Systems
• Multi-Service Edge Switches or Routers
• Multi-Service Provisioning Platforms (MSPPs)
• Add-Drop Multiplexers (ADMs)
• Wireless/Wireline Gateways
• Wireless Base Stations
• DSLAM / Next Gen DLC
• Core Routers


Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Fans, Thermal Management
3610ML-05W-B49
1608KL-05W-B39
Optoelectronics
SFH7770
TLP423J
Static Control, ESD, Clean Room Products
DPA5
PA800-A41
RF and RFID
X3C26P1-30S
1P620S
Test Equipment
TOP853
TOP2005
Semiconductor Modules
2DI300A-050-03
7MBR25SA-120-50
View more