ZL50012/QCC

• 512 channel x 512 channel non-blocking switch at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation
• Rate conversion between the ST-BUS inputs and ST-BUS outputs
• Per-stream ST-BUS input with data rate selection of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
• Per-stream ST-BUS output with data rate selection of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s; the output data rate can be different than the input data rate
• Per-stream high impedance control output for every ST-BUS output with fractional bit advancement
• Per-stream input channel and input bit delay programming with fractional bit delay
• Per-stream output channel and output bit delay programming with fractional bit advancement
• Multiple frame pulse outputs and reference clock outputs
• Per-channel constant throughput delay
• Per-channel high impedance output control
• Per-channel message mode
• Per-channel pseudo random bit sequence (PRBS) pattern generation and bit error detection
• Control interface compatible to Motorola nonmultiplexed CPUs
• Connection memory block programming capability
• IEEE-1149.1 (JTAG) test port
• 3.3V I/O with 5 V tolerant input

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

The ZL50012/QCC has sixteen ST-BUS inputs (STi0-15) and sixteen ST-BUS outputs (STo0-15). The ZL50012/QCC is a non-blocking digital switch with 512 64 kb/s channels and performs rate conversion between the ST-BUS inputs and ST-BUS outputs. The ST-BUS inputs accept serial input data streams with the data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s on a per-stream basis. The ST-BUS outputs deliver serial output data streams with the data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s on a per-stream basis. The ZL50012/QCC also provides sixteen high impedance control outputs (STOHZ 0-15) to support the use of external high impedance control buffers.

The ZL50012/QCC has features that are programmable on per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay and high impedance output control.