CY7C1354BV25

The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354BV25 and CY7C1356BV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1354BV25 and CY7C1356BV25 are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs of CY7C1354BV25 and CY7C1356BV25 pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input of CY7C1354BV25 and CY7C1356BV25 is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations of CY7C1354BV25 and CY7C1356BV25 are controlled  by the Byte Write Selects (BW_aBW_d for CY7C1354BV25 and BW_aBW_b for CY7C1356BV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CY7C1354BV25 and CY7C1356BV25(CE₁, CE₂, CE₃) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.