SN74ABT16823

Members of the Texas Instruments WidebusE Family
State-of-the-Art EPIC-IIBE BiCMOS Design Significantly Reduces Power Dissipation
High-Impedance State During Power Up and Power Down
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Typical VOLP (Output Ground Bounce) < 1 V at V_CC = 5 V, T_A = 25
Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB Layout
High-Drive Outputs (32-mA IOH, 64-mA IOL)
 Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, V_I (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V_O . . . . . . . . . . . .. . . . . . . 0.5 V to 5.5 V
Current into any output in the low state, I_O: SN54ABT16823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
                                                                       SN74ABT16823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I_IK (V_I < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . 18 mA
Output clamp current, I_OK (V_O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . 50 mA
Package thermal impedance, qJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81/W
                                                                          DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under  recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.

These 'ABT16823 18-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. 'ABT16823 are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The 'ABT16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock.

A buffered output-enable (OE) input of 'ABT16823can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.However, to ensure the high-impedance state of 'ABT16823 above 2.1 V, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.The SN54ABT16823 is characterized for operation over the full military temperature range of 55 to 125.The SN74ABT16823 is characterized for operation from 40 to 85.