USD352

The USD352 series of ULCs is well suited for conversion of large sized CPLDs andFPGAs. We can support within one ULC from 18 Kbits to 390 Kbits DPRAM and from46 Kgates to 780 Kgates. Typically, ULC die size is 50% smaller than the equivalentFPGA die size. DPRAM blocks are compatible with Xilinx or Altera FPGA blocks.Devices are implemented in highperformance CMOS technology with 0.35µm(drawn) channel lengths, and are capable of supporting flipflop toggle rates of 200MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V.

The architecture of the USD352 series allows for efficient conversion of many PLD archi-tecture and FPGA device types with higher IO count. A compact RAM cell, along withthe large number of available gates allows the implementation of RAM in FPGA archi-tectures that support this feature, as well as JTAG boundaryscan and scanpathtesting.

Conversion to the USD352 series of ULC can provide a significant reduction in operatingpower when compared to the original PLD or FPGA. This is especially true when com-pared to many PLD and CPLD architecture USD352, which typically consume 100mAor more even when not being clocked. The UA1 series has a very low standby con-sumption of 0.3nA/gate typically commercial temperature, which would yield astandby current of 42µA on a 144,000 gates design.

Operating consumption of USD352 is a strictfunction of clock frequency, which typically results in a power reduction of 50% to 90%depending on the device being compared.