79RC32438, 79RC324H434-400BCG, 79RC32H434 Selling Leads, Datasheet
MFG:N/A Package Cooled:N/A D/C:09+
79RC32438, 79RC324H434-400BCG, 79RC32H434 Datasheet download
Part Number: 79RC32438
MFG: N/A
Package Cooled: N/A
D/C: 09+
79RC32438, 79RC324H434-400BCG, 79RC32H434
- Table of contents:
Info of 79RC32438
Info of 79RC324H434-400BCG
Info of 79RC32H434
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About 79RC32438
PDF/DataSheet Download
Datasheet: 79RC32438
File Size: 660414 KB
Manufacturer: IDT [Integrated Device Technology]
Download : Click here to Download
About 79RC32332
PDF/DataSheet Download
Datasheet: 79RC32332
File Size: 433350 KB
Manufacturer: IDT
Download : Click here to Download
About 79RC32332
PDF/DataSheet Download
Datasheet: 79RC32332
File Size: 433350 KB
Manufacturer: IDT
Download : Click here to Download
79RC32438 Maximum Ratings
| Symbol | Parameter | Min1 | Max1 | Unit |
| VCCI/O | I/O supply except for SSTL_22 | -0.6 | 4.0 | V |
| VCCSI/O | I/O supply for SSTL_22 | -0.6 | 3.0 | V |
| VCCCore | Core Supply Voltage | -0.6 | 2.0 | V |
| VCCPLL | PLL supply | -0.6 | 2.0 | V |
| VinI/O | I/O Input Voltage except for SSTL_2 | -0.6 | VCCI/O+ 0.5 | V |
| VinSI/O | I/O Input Voltage for SSTL_2 | -0.6 | VCCSI/O+ 0.5 | V |
| Ta Industrial |
Ambient Operating Temperature | -40 | +85 | °C |
| Ta Commercial |
Ambient Operating Temperature | 0 | +70 | °C |
| Ts | Storage Temperature | -40 | +125 | °C |
79RC32438 Features
32-bit CPU Core
MIPS32 instruction set
Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches
16 dual-entry JTLB with variable page sizes
3-entry instruction TLB
3-entry data TLB
Max issue rate of one 32x16 multiply per clock
Max issue rate of one 32x32 multiply every other clock
CPU control with start, stop and single stepping
Software breakpoints support
Hardware breakpoints on virtual addresses
Enhanced JTAG and ICE Interface that is compatible with v2.5 of the EJTAG Specification
DDR Memory Controller
Supports up to 2GB of DDR SDRAM
2 chip selects (each chip select supports 4 internal DDR banks)
Supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit devices
Supports 64Mb, 128Mb, 256Mb, 512Mb, and 1Gb DDR SDRAM devices
Data bus multiplexing support allows interfacing to standard DDR DIMMs and SODIMMs
Automatic refresh generation
Memory and Peripheral Device Controller
Provides "glueless" interface to standard SRAM, Flash, ROM,dual-port memory, and peripheral devices
Demultiplexed address and data buses: 16-bit data bus, 26-bit address bus, 6 chip selects, supports alternate bus masters,control for external data bus buffers
Supports 8-bit and 16-bit width devices Automatic byte gathering and scattering
Flexible protocol configuration parameters: programmable number of wait states (0 to 63), programmable postread/post-write delay (0 to 31), supports
external wait state generation,supports Intel and Motorola style peripherals
Write protect capability per chip select
Programmable bus transaction timer generates warm reset when counter expires
Supports up to 64 MB of memory per chip select
Counter/Timers
Three general purpose 32-bit counter timers
PCI Interface
32-bit PCI revision 2.2 compliant (3.3V only)
Supports host or satellite operation in both master and target modes
Support for synchronous and asynchronous operation
PCI clock supports frequencies from 16 MHz to 66 MHz
PCI arbiter in Host mode: supports 6 external masters, fixed priority or round robin arbitration
I2O "like" PCI Messaging Unit
79RC32438 Connection Diagram
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