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These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs.
FDG6304P Maximum Ratings
Symbol
Parameter
Ratings
Units
VDSS VGSS
Drain-Source Voltage Gate-Source Voltage
-25 -8 -0.41 -1.5 0.3 -55 to 150 6.0
V V
A
W °C kV
ID
Drain Current Continuous Pulsed
PD
Power Dissipation for Single Operation
TJ, TSTG
Operating and Storage Junction Temperature Range
ESD
Electrostatic Discharge Rating MIL-STD-883D Human Body Model ( 100pF / 1500Ω )
THERMAL CHARACTERISTICS
RJA
Thermal Resistance, Junction-to-Ambient (Note 1)
415
°C/W
FDG6304P Features
·-25 V, -0.41 A continuous, -1.5 A peak. ·RDS(ON) = 1.1 W @ VGS= -4.5 V, ·RDS(ON) = 1.5 W @ VGS= -2.7 V. ·Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). ·Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). ·Compact industry standard SC70-6 surface mount package.