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QS5805, QS5805ASO, QS5805ATQ

Table of contents:
Info of QS5805
Info of QS5805ASO
Info of QS5805ATQ

QS5805, QS5805ASO, QS5805ATQ Selling Leads, Datasheet

MFG:IDT Package Cooled:SMD D/C:2007+

QS5805, QS5805ASO, QS5805ATQ Datasheet download

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Part Number: QS5805

MFG: IDT

Package Cooled: SMD

D/C: 2007+

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QS5805 General Description

The QS5805 clock buffer/driver circuits can be used for clock buffering schemes where low skew is a key parameter. This device offers two banks of five non-inverting outputs. The QS5805 device provides low propagation delay buffering with on-chip skew of 0.7ns for same-transition, same-bank signals.

The QS5805 is characterized for operation at -40°C to +85°C.

QS5805 Maximum Ratings

Rating	Symbol	Max	unit
Supply Voltage Range	V _CC1, V_CC2	0.5 to +4.6	V
Input Voltage Range	V_I⁽²⁾	0.5 to +5.5	V
Voltage range applied to any output in the high or low state	V_O⁽²⁾	0.5 to VDD + 0.5	V
Input clamp current	I_IK (VI < 0)	50	mA
Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5)	I_OK (V_O < 0 or V_O> V_DD)	-50	mA
Continuous Output Current	I_RES	±100	mA
Continuous Current	V_DDor G_ND	65 to +150	mA
Junction Temperature	T_STG	150	°C

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operation of the device at these any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.

QS5805 Features

- 10 CMOS outputs
- Monitor output
- Rail-to-rail output voltage swing
- Input hysteresis for better noise margin
- Guaranteed low skew:
· 0.7ns output skew (same bank)
· 0.8ns output skew (different banks)
· 1.2ns part-to-part skew
- Std., A, and B speed grades
- Available in QSOP and SOIC packages

QS5805 Connection Diagram

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