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QS5LV919-160J, QS5LV919-160Q, QS5LV931

Table of contents:
Info of QS5LV919-160J
Info of QS5LV919-160Q
Info of QS5LV931

QS5LV919-160J, QS5LV919-160Q, QS5LV931 Selling Leads, Datasheet

MFG:9 Package Cooled:IDT D/C:98

QS5LV919-160J, QS5LV919-160Q, QS5LV931 Picture

QS5LV919-160J, QS5LV919-160Q, QS5LV931 Datasheet download

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Part Number: QS5LV919-160J

MFG: 9

Package Cooled: IDT

D/C: 98

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QS5LV931 General Description

The QS5LV931 Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. Six outputs are available: Q0Q4, Q/2. Careful layout and design ensure <300ps skew between the Q0Q4, and Q/2 outputs. The QS5LV931 includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. The QS5LV931 is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5LV931 clock driver represents the best value in small form factor, high-performance clock management products.

For more information on PLL clock driver products, see Application Note AN-227.

QS5LV931 Features

• 3.3V operation
• JEDEC LVTTL compatible level
• Clock input is 5V tolerant
• Q outputs, Q/2 output
• <300ps output skew, Q0Q4
• Outputs 3-state and reset while OE/RST low
• PLL disable feature for low frequency testing
• Internal loop filter RC network
• Internal VCO/2 option
• Balanced drive outputs ±24mA
• ESD >2000V
• 80MHz maximum frequency
• Available in QSOP package

QS5LV931 Connection Diagram

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