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RM7000, RM7000-250, RM7000-2505

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Info of RM7000
Info of RM7000-250
Info of RM7000-2505

RM7000, RM7000-250, RM7000-2505 Selling Leads, Datasheet

MFG:PMC Package Cooled:BGA D/C:08+

RM7000, RM7000-250, RM7000-2505 Datasheet download

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Part Number: RM7000

MFG: PMC

Package Cooled: BGA

D/C: 08+

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RM7000 General Description

PMC-Sierra's RM7000 is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit. To keep its multiple execution units running efficiently, the RM7000 integrates not only 16 KB 4-way set associative instruction and data caches but backs them up with an integrated 256 KB 4-way set associative secondary as well. For maximum efficiency, the data and secondary caches are write-back and non-blocking. An optional external tertiary cache provides high-performance capability even in applications having very large data sets.

A RM5200 Family compatible, operating system friendlymemory management unit with a 64/48- entry fully associative TLB and a high-performance 64-bit system interface supporting multiple outstanding reads with out-of-order return and hardware prioritized and vectored interrupts round out the main features of the processor.

The RM7000 is ideally suited for high-end embedded control applications such as internetworking, high-performance image manipulation, high-speed printing, and 3-D visualization. The RM7000 is also applicable to the low end workstation market where its balanced integer and floating-point performance and direct support for a large tertiary cache (up to 8 MB) provide outstanding price/performance.

RM7000 Maximum Ratings

Symbol	Rating	Limits	Unit
V_TERM	Terminal Voltage with respect to Vss	0.5² to +3.9	V
T_CASE	Operating Temperature	0 to +85
T_STG	Storage Temperature	55 to +125
I_IN	DC Input Current³	±20	mA
I_OUT	DC Output Current⁴	±20	mA

Notes
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VIN minimum = -2.0 V for pulse width less than 15 ns. V_IN should not exceed 3.9 Volts.
3. When V_IN< 0V or V_IN> VccIO
4. Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.

RM7000 Features

• Dual Issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance
• 200, 250, 266, 300 MHz operating frequency
• >500 Dhrystone 2.1 MIPS @ 300 MHz
• High-performance system interface
• 1000 MB per second peak throughput
• 125 MHz max. freq., multiplexed address/data
• Supports two outstanding reads with out-of-order return
• Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9
• Integrated primary and secondary caches - all are 4-way set associative with 32 byte line size
• 16 KB instruction, 16 KB data, 256 KB on-chip secondary
• Per line cache locking in primaries and secondary
• Fast Packet Cache™ increases system efficiency in networking applications
• Integrated external cache controller (up to 8 MB)
• High-performance floating-point unit - 600 MFLOPS maximum
• Single cycle repeat rate for common single-precision operations and some double-precision operations
• Single cycle repeat rate for single-precision combined multiply-add operations
• Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations
• MIPS IV Superset Instruction Set Architecture
• Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution
• Single-cycle floating-point multiply-add
• Integrated memory management unit
• Fully associative joint TLB (shared by I and D translations)
• 64/48 dual entries map 128/96 pages
• Variable page size
• Embedded application enhancements
• Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and threeoperand multiply instruction (MUL)
• I&D Test/Break-point (Watch) registers for emulation & debug
• Performance counter for system and software tuning & debug
• Fourteen fully prioritized vectored interrupts - 10 external, 2 internal, 2 software
• Fully static CMOS design with dynamic power down logic
• RM5271 pin compatible, 304 pin TBGA package, 31x31 mm

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