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STLC5046S, STLC504BCP, STLC5411

Table of contents:
Info of STLC5046S
Info of STLC504BCP
Info of STLC5411

STLC5046S, STLC504BCP, STLC5411 Selling Leads, Datasheet

MFG:STM Package Cooled:QFP-64 D/C:00+

STLC5046S, STLC504BCP, STLC5411 Datasheet download

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Part Number: STLC5046S

MFG: STM

Package Cooled: QFP-64

D/C: 00+

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STLC5411 General Description

STLC5411 is a complete monolithic transceiver for ISDN Basic access data transmission on twisted pair subscriber loops typical of public switched telephone networks. The device is fully compatible with both ANSI T1.601-1988 U.S. and CSE (C32-11) French specifications. It is intended also to comply with ETSI specification both in term of transmission performances and requested features.

The equivalent of 160 kbit/s full-duplex transmission on a single twisted pair is provided, according to the formats defined in the a.m. spec.Frames include two B channels,each of 64 kbit/s,one D channel of 16 kbit/s plus an additional 4 kbit/s M channel for loop maintenance and other user functions. 12 kbit/s bandwidth is reserved for framing. 2B1Q Line coding is used, where pairs of bits are coded into one of 4 quantum levels. This technique results in a low frequency spectrum (160 kbit/s turn into 80 kband), thereby reducing both line attenuation and crosstalk and achieving long range with low Bit Error Rates.

The system is designed to operate on standard types of cable pairs including mixed gauges (26 AWG, 24 AWG and 22 AWG) including the 15 loops configuration specified by ANSI. Good noise margins are achieved even when bridged
taps are present. On 26 AWG cable, the transmission range is in excess of 5.5 km (18 kft) in presence of crosstalk and noise as specified by ANSI standard. STLC5411 is designed to operate with Bit Error Rate near-end Crosstalk (NEXT) as specified in european ETSI recommendation.To meet these very demanding specifications, the device includes two Digital Signal Processors,one configured as an adaptive Echo-Canceller to cancel the near end echoes resulting from the transmit/receive hybrid interface, the other as an adaptive line equalizer. A Digital Phase-Locked Loop (DPLL) timing recovery circuit is also included that provides in NT modes a 15.36 MHz synchronized clock to the rest of the system.Scrambling and descrambling are performed as specified in the US and French specifications.

On the system side, STLC5411 can be linked to two bus configuration simply by pin MWbias.

STLC5411 Maximum Ratings

Symbol	Parameter	Value	Unit
V_CC	Supply Voltage	0.3 to 7.0	V
V_I	Input Voltage	0.3 to 7.0	V
T_A	Operting Temperature Range	0 to 70	°C
Tstg	Storage Temperature Range	-65 to +150	°C

STLC5411 Features

SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER
SUITABLE FOR BOTH ISDN AND PAIR GAIN APPLICATIONS
MEETS OR EXCEEDS ANSI U.S. AND ETSI EUROPEAN STANDARD
SINGLE 5V SUPPLY
DIP28 AND PLCC44 PACKAGE
HCMOS3A SGS-THOMSON ADVANCED 1.2mm DOUBLE-METALCMOS PROCESS

STLC5411 Connection Diagram

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