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V54C365164VC, V54C365164VC17, V54C365164VC-6T

V54C365164VC, V54C365164VC17, V54C365164VC-6T Selling Leads, Datasheet

MFG:MOSEL  Package Cooled:TSSOP  D/C:07+

V54C365164VC, V54C365164VC17, V54C365164VC-6T Picture

V54C365164VC, V54C365164VC17, V54C365164VC-6T Datasheet download

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Part Number: V54C365164VC

 

MFG: MOSEL

Package Cooled: TSSOP

D/C: 07+

 

 

 
 
 
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About V54C365164VC

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Datasheet: V54C365164VC

File Size: 1608577 KB

Manufacturer: MOSEL [Mosel Vitelic, Corp]

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About V54C3128

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Datasheet: V54C3128

File Size: 892430 KB

Manufacturer: MOSEL [Mosel Vitelic, Corp]

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About V54C3128

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Datasheet: V54C3128

File Size: 892430 KB

Manufacturer: MOSEL [Mosel Vitelic, Corp]

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V54C365164VC General Description

The V54C365164VC is a four bank Synchronous DRAM organized as 4 banks x 1Mbit x 16. The V54C365164VC achieves high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock

All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is possible depending on burst length, CAS latency and speed grade of the device.

V54C365164VC Maximum Ratings

Operating temperature range .............................................0 to 70 °C
Storage temperature range .......................................... -55 to 150 °C
Input/output voltage ............................................ -0.3 to (VCC+0.3) V
Power supply voltage ...................................................... -0.3 to 4.6 V
Power dissipation .......................................................................... 1 W
Data out current (short circuit) ................................................... 50 mA

V54C365164VC Features

4 banks x 1Mbit x 16 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signalsreferenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for byte Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 1, 2, & 3
Programmable Wrap Sequence: Sequential or Interleave
Programmable Burst Length:
  1, 2, 4, 8 and full page for Sequential Type
  1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Suspend Mode and Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 54 Pin 400 mil TSOP-II
LVTTL Interface
 Single +3.3 V± 0.3 V Power Supply

V54C365164VC Connection Diagram

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