VG-365A100, VG365B, VG36641641DT Selling Leads, Datasheet
MFG:VADEM Package Cooled:PLCC D/C:1993
VG-365A100, VG365B, VG36641641DT Datasheet download
Part Number: VG-365A100
MFG: VADEM
Package Cooled: PLCC
D/C: 1993
VG-365A100, VG365B, VG36641641DT
- Table of contents:
Info of VG-365A100
Info of VG365B
Info of VG36641641DT
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Datasheet: VG-1011JA
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Manufacturer: ETC [ETC]
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About VG36641641DT
PDF/DataSheet Download
Datasheet: VG36641641DT
File Size: 1397574 KB
Manufacturer: ETC [ETC]
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VG36641641DT General Description
The VG36644041D, VG36648041D and VG36641641D are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4 and 1,048,576 x 16 x4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
VG36641641DT Maximum Ratings
| Parameter |
Symbol |
Conditions |
Value |
Unit |
| Supply Voltage |
VDD |
with respect to VSS |
-0.5 to 4.6 |
V |
| Supply Voltage for Output |
VDDQ |
with respect to VSSQ |
-0.5 to 4.6 |
V |
| Input Voltage |
VI |
with respect to VSS |
-0.5 to VDD+0.5 |
V |
| Output Voltage |
VO |
with respect to VSSQ |
-0.5 to VDDQ+0.5 |
V |
| Short circuit output current |
IO |
50 |
mA | |
| Power dissipation |
PD |
Ta = 25 °C |
1 |
W |
| Operating temperature |
TOPT |
0 to 70 |
||
| Storage temperature |
TSTG |
-65 to 150 |
VG36641641DT Features
• Single 3.3V ( ±0.3V ) power supply
• High speed clock cycle time
-6 : 166MHz<3-3-3>, available only on 4MX16 option
-7 : 143MHz<3-3-3>, 133MHz<2-3-2>
-7L: 133MHz<3-3-3>
-8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by A12 & A13 (Bank Select)
• Byte control by LDQM and UDQM for VG36641641D
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command
• High speed clock cycle time
-6 : 166MHz<3-3-3>, available only on 4MX16 option
-7 : 143MHz<3-3-3>, 133MHz<2-3-2>
-7L: 133MHz<3-3-3>
-8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by A12 & A13 (Bank Select)
• Byte control by LDQM and UDQM for VG36641641D
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command
VG36641641DT Connection Diagram
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