VG330, VG357-E3, VG36128161BT Selling Leads, Datasheet
MFG:VADEM Package Cooled:QFP D/C:99+
VG330, VG357-E3, VG36128161BT Datasheet download
Part Number: VG330
MFG: VADEM
Package Cooled: QFP
D/C: 99+
VG330, VG357-E3, VG36128161BT
- Table of contents:
Info of VG330
Info of VG357-E3
Info of VG36128161BT
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About VG36128161A
PDF/DataSheet Download
Datasheet: VG36128161A
File Size: 963545 KB
Manufacturer: VML [Vanguard International Semiconductor]
Download : Click here to Download
About VG36128161A
PDF/DataSheet Download
Datasheet: VG36128161A
File Size: 963545 KB
Manufacturer: VML [Vanguard International Semiconductor]
Download : Click here to Download
About VG36128161BT
PDF/DataSheet Download
Datasheet: VG36128161BT
File Size: 1390076 KB
Manufacturer: VML [Vanguard International Semiconductor]
Download : Click here to Download
VG36128161BT General Description
The VG36128401B, VG36128801B and VG3664128161B are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 x 4 x 4, 4,194,304 x 8 x 4 and 2,097,152 x16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
VG36128161BT Maximum Ratings
| Parameter |
Symbol |
Conditions |
Value |
Unit |
| Supply Voltage |
VDD |
with respect to VSS |
-0.5 to 4.6 |
V |
| Supply Voltage for Output |
VDDQ |
with respect to VSSQ |
-0.5 to 4.6 |
V |
| Input Voltage |
VI |
with respect to VSS |
-0.5 to 4.6 |
V |
| Output Voltage |
VO |
with respect to VSSQ |
-0.5 to 4.6 |
V |
| Short circuit output current |
IO |
50 |
mA | |
| Power dissipation |
PD |
Ta = 25 °C |
1 |
W |
| Operating temperature |
TOPT |
0 to 70 |
||
| Storage temperature |
TSTG |
-65 to 150 |
VG36128161BT Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM for VG36128161DT
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• High speed clock cycle time -7H: 133MHz<2-2-2>, -7L: 133MHz<3-3-3>, -8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by BA0 & BA1 (Bank Select)
• Byte control by LDQM and UDQM for VG36128161DT
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
VG36128161BT Connection Diagram
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