Published:2011/8/1 20:52:00 Author:Lucas | Keyword: 74 Series , digital circuit, 8-bit shift register | From:SeekIC
Parallel storage; right shift(direction is from the QA to QH): left shift(direction is from the QH to QA); it forbids the clock.a. .. h= the input of steady-state input level of A to H.QAo, QBo, QGo, QHo=the corresponding level level of QA, QB, QG, QH before building the specified steady state.QAn, QBn..QGn= the corresponding level of QA, QB to QGbefore the next jump of the clock.
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