74 Series digital circuit of 74LS354/356 8-to-1 data selector(tristate with address latching)

Published:2011/8/2 0:43:00 Author:Lucas | Keyword: 74 Series, digital circuit , 8-to-1 data selector, tristate , address latching | From:SeekIC

This list shows that the input address is established when the control is low. D1 ~ D7 are the data input. D0n ~ D7n are the steady state input level in D0 ~ D7 line before the latest increasing of the data control or clock pulse. Three-state output with address latching; data register can choose data latch(354) or edge-triggered (356).



Reprinted Url Of This Article:
http://www.seekic.com/circuit_diagram/Basic_Circuit/Digital_Circuit/74_Series_digital_circuit_of_74LS354_356_8_to_1_data_selectortristate_with_address_latching.html

Print this Page | Comments | Reading(3)