ADJUSTABLE_TTL_CLOCK（MAINTAINS_50％DUTY_CYCLE）

Published:2009/6/25 21:25:00 Author:May | From:SeekIC

Symmetry of the square-wave output is maintained by connecting the right side of R2 through resistor R3 to the output of the third amplifier stage. This changes the charging cur-rent to the capacitors in proportion to the set-ting of frequency-adjusting potentiometer R2. Thus, a duty cycle of 50% is constant over the entire range of oscillation. The lower frequency limit is set by capacitor C2. With the components shown, the frequency of oscilla-tion can be varied by R2 from about 4 to 20 hertz. Other frequency ranges can be obtained by changing the values of C1 and R3, which control the upper limit of oscillation, or C2, which limits the low-frequency end.



Reprinted Url Of This Article:
http://www.seekic.com/circuit_diagram/Basic_Circuit/Digital_Circuit/ADJUSTABLE_TTL_CLOCK（MAINTAINS_50％DUTY_CYCLE）.html

Print this Page | Comments | Reading(3)