LEADING_EDGE_DELAY

Published:2009/7/7 8:42:00 Author:May | From:SeekIC

Circuit (a) lets you delay the leading edge of a positive pulse while leaving the trailing edge almost unaffected. A positive input transition, inverted by IC2, has no effect on IC1B. However, when the positive transition reaches IC1A, (delayed by the adjustable network of R1, R2, and C1), it toggles both NOR gates, initiating the output pulse. When the input decreases IC1B follows suit, delayed only by the propagation through itself and IC2. Circuit (b) produces an inverted output pulse. Inverter IC1 serves as a buffer for the signal source-an advantage when driving a low-impedance (short-delay) network. Moreover, only the propagation delay of IC2B separates the output's trailing edge from that of the input. You can configure circuit (a) to handle negative pulses by using NAND instead of NOR gates. Similarly, circuit (b) will produce a delayed positive pulse in response to negative input pulse, if you substitute NOR gates for NAND gates.



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