S_R_FLIP_FLOP

Published:2009/7/12 21:13:00 Author:May | From:SeekIC

This circuit combines the characteristics of an asynchronous S/R flip-flop and an edge-triggered JK flip-flop. It changes state on the leading edges of its inputs, and ignores the levels at all other times.In operation, outputs of both D flip-flops are normally high, going low for brief periods after seeing an edge at their respective clock inputs.



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